Large and Fast: Exploiting Memory Hierarchy

What is the term for the principle stating that if an item is referenced, items whose addresses are close by will tend to be referenced soon?

What is the term for the minimum unit of information that can be either present or not present in a cache?

According to the memory technology table from 2012, what was the typical cost per GiB for DRAM semiconductor memory?

How is the average rotational latency of a disk calculated?

What is the name of the cache structure in which each memory location is mapped to exactly one location in the cache?

For a direct-mapped cache with 16 KiB of data, 64-bit addresses, and four-word blocks, how many total Kibibits are required for the entire cache structure, including data, tags, and the valid bit?

For a cache with 64 blocks and a block size of 16 bytes, to what block number does byte address 1200 map?

Which scheme handles writes by updating values only to the block in the cache, and then writing the modified block to the lower level of the hierarchy when the block is replaced?

What is the formula for Average Memory Access Time (AMAT)?

In a cache with eight total blocks, how many sets would a two-way set-associative cache have?

A processor has a base CPI of 1.0, a 4 GHz clock rate, and a primary cache miss rate per instruction of 2 percent. If main memory access time is 100 ns, what is the total CPI including memory stalls?

In the 'Three Cs' model of cache misses, what type of miss is caused by the first access to a block that has never been in the cache?

Given a disk with a Mean Time To Failure (MTTF) of 1,000,000 hours, what is its approximate Annual Failure Rate (AFR)?

In the context of virtual memory, what is an event that occurs when an accessed page is not present in main memory called?

What is the primary function of a Translation-Lookaside Buffer (TLB)?

To enable an operating system to implement memory protection, what must the hardware provide?

What is the term for the problem where two different processors, through their individual caches, could see two different values for the same memory location?

What is the fundamental action of a write invalidate protocol when one processor performs a write to a data item?

What is the primary drawback of RAID 4 that RAID 5 aims to solve by distributing parity blocks?

What is false sharing in the context of a cache coherent multiprocessor?

Which of the following cache design choices most directly exploits spatial locality?

What is the primary motivation for using a write buffer?

Which of the following is a key reason that DRAM is less costly per bit than SRAM?

What does the replacement policy 'Least Recently Used' (LRU) dictate?

To provide Single Error Correction (SEC) for an 8-bit data word, how many parity bits are required according to the formula given?

In a virtual memory system, what is the purpose of the dirty bit associated with a page table entry?

A miss that occurs in a set-associative cache because multiple blocks compete for the same set, which would have been avoided in a fully associative cache of the same size, is called what?

A processor with a base CPI of 2 and a miss penalty of 100 cycles experiences a 2 percent instruction cache miss rate and a 4 percent data cache miss rate. If 36 percent of all instructions are loads and stores, what is the total CPI including memory stalls?

For a cache of 4096 blocks, a four-word block size, and a 64-bit address, what is the total number of tag bits required for a two-way set-associative configuration?

Which memory hierarchy write policy simplifies handling cache misses because it never requires a block to be written back to the lower level?

What is the primary advantage of using split instruction and data caches over a single unified cache of the same total size?

In the simple four-state cache controller FSM described in Section 5.9, what state is responsible for writing a dirty block back to memory before allocating space for a new block?

To perform a 'small write' in a RAID 5 system, how many disk accesses are required?

What is a primary motivation for using large page sizes in virtual memory systems?

Find the Average Memory Access Time (AMAT) for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time of 1 clock cycle.

In the RISC-V virtual memory example from Figure 5.26, a 48-bit virtual address is mapped to a 40-bit physical address. What does this imply about the relative sizes of the total virtual and physical address spaces?

What is a potential negative performance effect of increasing the cache block size?

What is the term for the memory system property that defines what values can be returned by a read in a multiprocessor system?

What design feature gives a direct-mapped cache a potential advantage in access time over a set-associative cache?

In a multilevel cache hierarchy, what is the typical design focus for the primary (L1) cache?

What is the minimum Hamming distance required for a code to be able to correct single-bit errors?

If a data center has 50,000 servers, each with two disks, and each disk has an MTTF of 1,000,000 hours, approximately how many disks would be expected to fail per year?

What is the primary goal of using blocked algorithms for matrix operations?

In the Intrinsity FastMATH processor, how are TLB misses handled?

In which of the following scenarios is a memory access guaranteed to be an impossibility?

A cache that is accessed with a virtual address for the index but uses physical addresses for the tags is known as what?

What is the key difference between a Moore and a Mealy finite-state machine?

What is the term for a cache miss that is caused by the cache being too small to contain all the blocks needed during a program's execution, even with full associativity?

Which of the following is an advantage of a write-back cache policy compared to a write-through policy?

In a multilevel cache system, what is the 'local miss rate' of the L2 cache?