Arithmetic for Computers

Under what condition does overflow occur during the addition of two positive 64-bit two's complement numbers?

When can overflow NOT occur during the subtraction of two's complement numbers?

If an n-bit multiplicand is multiplied by an m-bit multiplier, what is the required length of the product in bits, not including sign bits?

In the sequential multiplication algorithm described, what action is determined by the least significant bit of the Multiplier register in each step?

Which RISC-V instruction is used to obtain the upper 64 bits from the 128-bit product of two signed 64-bit operands?

In the context of the division operation, what is the specific term for the number that the dividend is divided by?

What is the established rule for determining the sign of a non-zero remainder in a signed division operation?

What term is used to describe a number in scientific notation that has no leading zeros, such as 1.0 x 10 to the power of -9?

What is the value of the bias used for single-precision floating-point numbers in the IEEE 754 standard?

In the IEEE 754 standard, what is the value of the exponent bias for double-precision floating-point numbers?

In the IEEE 754 standard, what special value is used to represent the result of an invalid operation, such as subtracting infinity from infinity?

What is the first step in the algorithm for adding two floating-point numbers?

When multiplying two floating-point numbers represented with biased exponents, how is the new exponent calculated?

What is the primary precision advantage of using a fused multiply-add (FMA) instruction?

Using subword parallelism, how many simultaneous operations on 16-bit operands can be performed within a 128-bit adder?

In the context of x86 SSE/SSE2 instructions, what does the 'PS' suffix, such as in the ADDPS instruction, signify?

What was the key architectural enhancement introduced by Intel's Advanced Vector Extensions (AVX) compared to the preceding SSE instructions?

Which fundamental mathematical property does floating-point addition fail to uphold, as demonstrated by the example where ((-1.5 * 10 to the power of 38) + (1.5 * 10 to the power of 38)) + 1.0 yields a different result than (-1.5 * 10 to the power of 38) + ((1.5 * 10 to the power of 38) + 1.0)?

What was the specific technical cause of the highly publicized Intel Pentium floating-point divide bug of 1994?

According to the overflow conditions for addition and subtraction, which of these operations on Operand A and Operand B can result in an overflow?

What is the approximate range of numbers that can be represented using RISC-V double-precision floating-point format?

In the IEEE 754 standard for floating-point numbers, why is the leading 1 bit of a normalized binary number made implicit?

What is the name of the compiler optimization technique that replaces a multiplication by a power of 2 with a more efficient shift instruction?

In addition to doubling the register width to 256 bits, what new instruction format did the Advanced Vector Extensions (AVX) introduce to the x86 architecture?

What are the names of the two extra bits that the IEEE 754 standard mandates be kept on the right during intermediate floating-point calculations to improve rounding accuracy?

What does the 'sticky bit' help the computer to distinguish between when performing floating-point rounding?

Which RISC-V instructions are used to handle division and remainder for unsigned integers?

What is the primary purpose of a 'carry lookahead' adder design?

What does the term 'saturating arithmetic' refer to?

According to the refined multiplication hardware shown in Figure 3.5, where is the multiplier initially placed?

In the IEEE 754 standard, what is the object represented when the exponent field is all ones and the fraction field is non-zero?

The x86 vbroadcastsd instruction, used in the optimized DGEMM example, performs what function?

What is a 'fallacy' regarding the use of a right shift instruction for integer division?

In the refined division hardware (Figure 3.11), how is the Quotient register implemented?

What is the primary advantage of double-precision floating-point numbers over single-precision?

What does the RISC-V `remu` instruction compute?

In the DGEMM example, the unoptimized C code is improved by using C intrinsics. What is the purpose of the `_mm256_load_pd()` intrinsic?

The term 'gradual underflow' in the IEEE 754 standard is enabled by the use of what type of numbers?

What is the function of the `fmadd.d` instruction in the RISC-V floating-point extension?

When comparing the optimized AVX version of DGEMM to the unoptimized version on a 2.6 GHz Intel Core i7, what was the approximate speedup factor?

What is the decimal value of the hexadecimal number 0C000000 if it represents a 32-bit two's complement integer?

What decimal number is represented by the 32-bit single precision float with the binary representation '1 10000001 01000000000000000000000'?

In the RISC-V floating-point architecture, what is a key difference between integer register x0 and floating-point register f0?

What is the result of multiplying the 4-bit numbers 0010 (2) and 0011 (3) using the sequential algorithm from Figure 3.4?

What does the 'ulp' (units in the last place) measure in the context of floating-point arithmetic?

According to the IEEE 754 standard, how should a rounding case that is exactly halfway between two representable numbers be handled?

What is the binary representation of -0.75 in single-precision IEEE 754 format?

In the x86 instruction set, what does the suffix 'SD' signify in an instruction like `ADDSD`?

What is the Big Picture concept reinforced by the fact that the same bit pattern can represent a signed integer, an unsigned integer, or a floating-point number?

What architectural issue with the IBM S/360 and Cray computers, which was avoided in the IEEE 754 standard, caused rounding errors in addition and subtraction?