Question 42 of 50

What are the four primary terminals of an n-channel enhancement-mode MOSFET (NMOS) as described in its physical structure?

In an NMOS transistor, what is the effect of applying a sufficiently large positive voltage to the gate relative to the source?

An NMOS transistor is in the cutoff region of operation under what condition?

An NMOS transistor operates in the triode region when which two conditions are met?

An NMOS transistor has a process parameter KP = 50 microA/V^2, a width W = 80 micrometer, and a length L = 2 micrometer. Calculate the device constant K.

An enhancement-mode NMOS transistor has a device constant K = 2 mA/V^2 and a threshold voltage Vto = 2 V. If it operates in saturation with a gate-to-source voltage VGS = 4 V, what is the drain current iD?

What equation describes the boundary between the triode and saturation regions for an NMOS transistor?

Consider an NMOS transistor with Vto = 2 V. What is its region of operation if vGS = 3 V and vDS = 0.5 V?

How do the characteristics of a PMOS transistor generally compare to those of an NMOS transistor?

In the context of a simple NMOS amplifier circuit analyzed using a load-line, what is the quiescent operating point (Q point)?

For a simple NMOS amplifier with a supply voltage VDD = 20 V and a drain resistor RD = 1 kOhm, what is the equation for the load line?

In the load-line analysis of the NMOS amplifier in Figure 11.11, the quiescent operating point is found to be IDQ = 9 mA and VDSQ = 11 V. What is the cause of the nonlinear distortion observed in the output waveform?

What is the primary purpose of a bias circuit in a FET amplifier?

In a fixed-plus self-bias circuit like the one in Figure 11.13, what is the Thévenin voltage (VG) at the gate of the NMOS transistor?

In the fixed-plus self-bias circuit of Figure 11.15, VDD is +20 V, R1 is 3 MOhm, and R2 is 1 MOhm. What is the Thévenin equivalent voltage VG at the gate?

In a fixed-plus self-bias circuit, the relationship between the gate voltage, gate-to-source voltage, and drain current is described by the bias line equation. What is this equation?

For small-signal analysis of a FET, the transistor is modeled by a voltage-controlled current source connected between which two terminals?

The transconductance (gm) of a FET is an important small-signal parameter. How is gm defined in terms of the quiescent drain current (IDQ) and the device constant (K)?

A FET has a quiescent drain current IDQ = 0.784 mA. The transistor has parameters KP = 50 microA/V^2, W = 400 micrometer, and L = 10 micrometer. What is its transconductance gm?

What is the purpose of the small-signal drain resistance (rd) in a more complex FET equivalent circuit?

In a common-source amplifier's small-signal equivalent circuit, how is the DC supply voltage VDD treated?

What is the formula for the voltage gain (Av) of a common-source amplifier, assuming an ideal transistor model where rd is infinite?

A common-source amplifier has a transconductance gm = 1.77 mS. The drain resistor RD is 4.7 kOhm and the load resistor RL is 10 kOhm. Assuming the internal drain resistance rd is infinite, what is the midband voltage gain Av?

What is the input resistance (Rin) of a common-source amplifier with a four-resistor bias network consisting of R1 and R2 connected to the gate?

What is the primary effect of having an unbypassed source resistor (impedance between the FET source terminal and ground) in a common-source amplifier?

A source follower amplifier is also known as what type of amplifier configuration?

Which statement accurately describes the typical voltage gain characteristics of a source follower amplifier?

What is a primary reason for using a source follower amplifier in a circuit design?

A source follower has a transistor with gm = 8.944 mS and rd = infinity. Its biasing source resistor RS is 426.4 Ohm and the load RL is 1 kOhm. What is the approximate voltage gain Av?

A source follower amplifier has an input resistance of 1 MOhm and a load resistance of 1 kOhm. Its voltage gain is 0.7272. What is its current gain Ai?

In a CMOS inverter circuit, what happens when the input voltage Vin is high (equal to VDD)?

In a CMOS inverter circuit, what happens when the input voltage Vin is low (equal to 0)?

How are the transistors arranged in a two-input CMOS NAND gate?

In a two-input CMOS NAND gate, when is the output LOW?

How are the transistors arranged in a two-input CMOS NOR gate?

In a two-input CMOS NOR gate, when is the output HIGH?

The small-signal parameter gm can be defined as a partial derivative. What is this definition?

What is the primary factor that determines the value of KP (the device parameter) for a MOSFET?

A certain PMOS transistor has KP = 25 microA/V^2, Vto = -1 V, L = 2 micrometer, and W = 200 micrometer. What is its device constant K?

A PMOS transistor has KP = 25 microA/V^2, Vto = -1 V, L = 2 micrometer, and W = 200 micrometer. What is its device constant K?

What is channel-length modulation in a MOSFET?

How is the output resistance (Ro) of a common-source amplifier determined from its small-signal equivalent circuit, assuming the load is disconnected?

Even though a source follower has a voltage gain less than unity, how can it still provide significant power gain?

What is the key feature of a common-gate amplifier configuration as described in Exercise 11.13?

In a three-input CMOS NOR gate as shown in Figure 11.35, how are the PMOS transistors configured?

What is the primary reason that FET amplifier analysis is often undertaken in two steps: DC analysis and small-signal analysis?

How does the transconductance (gm) of a FET change if the quiescent drain current (IDQ) is increased?

Why is the body of an NMOS transistor sometimes called the substrate?

What is the primary reason complex digital circuits like microprocessors are often implemented solely with MOSFETs rather than BJTs?